The effect of ILD material and BPSG densification anneal on the device characteristics

Author

Jung, Jong-wan ; Lee, Young-Jong ; Hwang, Jeong-Mo ; Lee, Kyung-Ho

Author_Institution

Hyundai Micro Electron. Co. Ltd., Cheongju, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

473

Lastpage

475

Abstract

We examined the effect of inter-level dielectric (ILD) and densification anneal on device characteristics, such as polysilicon (poly-Si) activation, silicide resistance, and gate oxide integrity (GOI). For the sample with PTEOS/USG/PTEOS as ILD, any significant degradation of poly-Si activation and silicide resistance was not observed. But gate oxide was severely damaged due to PID. On the other hand, the sample with HLD/BPSG/PTEOS as ILD was free from PID. However, the poly-Si activation and silicide resistance significantly varied depending on the BPSG densification anneal. Our results shows that we should make a compromise between the dopant activation and silicide resistance

Keywords

CMOS integrated circuits; annealing; borosilicate glasses; densification; dielectric thin films; integrated circuit metallisation; phosphosilicate glasses; B2O3-P2O5-SiO2; BPSG; BPSG densification; ILD material; PID; PTEOS/USG/PTEOS; Si; device characteristics; dopant activation; gate oxide integrity; inter-level dielectric; poly-Si activation; polysilicon activation; silicide resistance; Annealing; CMOS technology; Degradation; Furnaces; Heat treatment; Plasma density; Plasma measurements; Plasma temperature; Resistance heating; Silicides;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5727-2

Type

conf

DOI

10.1109/ICVC.1999.820972

Filename

820972