Title :
A serial-parallel multiplier that accepts the MSB of the serial input first
Author :
du Plessis, W.P. ; Schoeman, J.
Author_Institution :
Dept. of Electr. & Electron. Eng., Pretoria Univ., South Africa
fDate :
6/21/1905 12:00:00 AM
Abstract :
A new serial-parallel multiplier structure that accepts the MSB of the serial input first is proposed. This approach results in a very small multiplier that produces the output with the shortest possible delay after the full input becomes available, when the serial input starts with the MSB
Keywords :
digital arithmetic; multiplying circuits; MSB; delay; most significant bit; serial input; serial-parallel multiplier; Acquired immune deficiency syndrome; Africa; Analog-digital conversion; Clocks; Delay systems; Field programmable gate arrays; Flip-flops; Logic; Propagation delay; Shift registers;
Conference_Titel :
Africon, 1999 IEEE
Conference_Location :
Cape Town
Print_ISBN :
0-7803-5546-6
DOI :
10.1109/AFRCON.1999.820979
