Title :
Implementing a timing shell for VHDL simulation using the proposed EIA-567 standard
Author :
McKinney, Michael D.
Author_Institution :
Lewis Systems, Inc., Irving, TX, USA
Abstract :
Timing issues in VHDL simulation continue to be important to the VHDL community. The proposed EIA-567 standard is one of several methods of describing a database for timing parameters within the language. Although there are several methods for accessing and using these data, the author explains how a particular timing shell was constructed, how it is used, its unique language constructs, and some singificant benefits of using this implementation
Keywords :
hardware description languages; logic CAD; standards; timing; EIA-567 standard; VHDL simulation; language constructs; timing parameters; timing shell; Data structures; Databases; Electronics packaging; Hardware design languages; Strontium; Systems engineering and theory; Technological innovation; Testing; Timing; Very high speed integrated circuits;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410724
