Fault sensitivity analysis of a 32-bit RISC microprocessor

This paper describes fault sensitivity analysis of a 32-bit RISC microprocessor. Logic-level transient faults are injected into the processor design that models an instruction subset of the MIPS R2000/3000 microprocessor. The processor model consists of gate-level Verilog HDL descriptions of pipeline datapath and behavioral models including memory system and register file. Faults are injected into the gate-level part of the design, and simulation is performed with the workload of four integer application programs. During simulation, fault manifestation and error propagation are monitored for key functional units of the pipeline datapath. For fault sensitivity analysis, the monitored data are categorized into pre-defined error classes. The experimental results show that the program counter is highly sensitive to transient faults, i.e., over 60% of injected faults resulted in fatal errors which caused the abnormal program terminations. This result suggests that incorporating fault-tolerant mechanisms into the program counter unit is highly desirable for mission-critical applications