Title :
Quaternary High Performance Arithmetic Logic Unit Design
Author :
Nagamani, A.N. ; Nishchai, S.
Author_Institution :
PES Inst. of Technol., Bangalore, India
Abstract :
Arithmetic operations in digital signal processing applications suffer from problems including propagation delay and circuit complexity. QSD number representation allows a method of fast addition/subtraction because the carry propagation chains are eliminated and hence it reduces the propagation time in comparison with common radix 2 system. Here we propose an arithmetic unit based on QSD number system based on quaternary system. The proposed design is developed using VHDL and implemented on FPGA device and results are compared with conventional arithmetic unit. The implementation of quaternary addition and multiplication results in a fix delay independent of the number of digits. Operations on a large number of digits such as 64, 128, or more, can be implemented with constant delay and less complexity.
Keywords :
circuit complexity; digital arithmetic; field programmable gate arrays; hardware description languages; multiprocessing systems; signal processing; FPGA device; QSD number representation; VHDL; arithmetic logic unit design; arithmetic operation; circuit complexity; digital signal processing application; quaternary system; radix 2 system; Adders; Delay; Field programmable gate arrays; Generators; Inverters; Table lookup; FPGA-Field Programmable Gate Arrays; QSD – quaternary signed digit; VHDL-VHSIC Hardware Description Language;
Conference_Titel :
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location :
Oulu
Print_ISBN :
978-1-4577-1048-3
DOI :
10.1109/DSD.2011.23
