Code generation of data dominated DSP applications for FPGA targets

Author

Dalcolmo, Josef ; Lauwereins, Rudy ; Adé, Marleen

Author_Institution

ESAT, Katholieke Univ., Leuven, Heverlee, Belgium

fYear

1998

Firstpage

162

Lastpage

167

Abstract

The VHDL code generator of the GRAPE rapid prototyping and design environment has been extended to support a much wider range of data dominated applications. We describe the approach taken to implement CSDF applications on FPGAs, including the automatic code generation for task communication and scheduling on FPGAs alone or in conjunction with DSP processors. The implementation choices are discussed, and a comparison to manual code generation is made

Keywords

application generators; field programmable gate arrays; hardware description languages; signal processing; software prototyping; CSDF applications; DSP processors; FPGA targets; GRAPE rapid prototyping; VHDL code generator; automatic code generation; code generation; data dominated DSP applications; design environment; implementation choices; scheduling; task communication; Application software; Automatic control; Computer architecture; Digital signal processing; Field programmable gate arrays; Flow graphs; Hardware; Identity-based encryption; Pipelines; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Rapid System Prototyping, 1998. Proceedings. 1998 Ninth International Workshop on

Conference_Location

Leuven

ISSN

1074-6005

Print_ISBN

0-8186-8479-8

Type

conf

DOI

10.1109/IWRSP.1998.676686

Filename

676686