Title :
A novel charge pump PLL with reduced jitter characteristics
Author :
Lee, Myoung-Su ; Cheung, Tae-Sik ; Choi, Woo-Young
Author_Institution :
Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 μm CMOS process technology and evaluated by post-layout simulation
Keywords :
CMOS analogue integrated circuits; jitter; phase locked loops; 0.6 micron; CMOS process technology; charge pump; control voltage leakage current; jitter characteristics; low-power design; phase locked loop; post-layout simulation; self-biased method; CMOS process; Charge pumps; Filters; Frequency conversion; Jitter; Logic; Phase frequency detector; Phase locked loops; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
DOI :
10.1109/ICVC.1999.821010
