Title :
10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard
Author :
Maistri, Paolo ; Leveugle, Régis
Author_Institution :
TIMA Lab., Grenoble INP, Grenoble, France
Abstract :
Current secure applications often need encrypted channels with high throughput, of the order of several gigabits per second. This level of performance is usually obtained with a considerable cost in terms of silicon area. In this paper, we present an implementation of the Advanced Encryption Standard based on heavy pipelining and partial unrolling, which is capable of a 10-Gbps throughput when encrypting with 128-bit keys.
Keywords :
cryptography; advanced encryption standard; bit rate 10 Gbit/s; encrypted channel; hardware implementation; heavy pipelining; high throughput; partial unrolling; secure application; silicon area; Computer architecture; Encryption; Optimization; Pipeline processing; Radiation detectors; Throughput; AES; ASIC; Counter Mode; Low gate count; Multi-gigabit throughput;
Conference_Titel :
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location :
Oulu
Print_ISBN :
978-1-4577-1048-3
DOI :
10.1109/DSD.2011.37
