Title :
Swallow counterless DMP PLL
Author :
Kim, Taewoo ; Lee, Soonseob ; Choi, Gwangseog ; Kim, Soowon ; Kim, Taegeun
Author_Institution :
Dept. of EE, Korea Univ., Seoul, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper proposes a new simple architecture of digital dividing system in dual-modulus prescaler phase-locked loop for wireless communications. In this new architecture a swallow counter is not employed while the same total division ratio as in a conventional system can be obtained. This simple architecture shows advantages in reducing power consumption and gate-counts and is suitable for small die area and low power applications. The circuit is designed in a standard 0.35 um CMOS process
Keywords :
CMOS digital integrated circuits; digital phase locked loops; dividing circuits; low-power electronics; mobile communication; prescalers; 0.35 micron; CMOS process; die area; digital dividing system; dual-modulus prescaler phase-locked loop; low power applications; power consumption; total division ratio; wireless communications; Application specific integrated circuits; Counting circuits; Detectors; Electronic mail; Energy consumption; Frequency conversion; Frequency synthesizers; Phase locked loops; Voltage-controlled oscillators; Wireless communication;
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
DOI :
10.1109/ICVC.1999.821013
