Title :
Double precharge TSPC for high-speed dual-modulus prescaler
Author :
Chae, Kwan-Yeob ; Ki, Hoon-Jae ; Hwang, In-Chul ; Kim, Soo-Won
Author_Institution :
Dept. of EE, Korea Univ., Seoul, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
A double precharge TSPC D-flip-flop (DFF) is proposed and a 3 GHz dual-modulus prescaler using the double precharge TSPC in 0.35 μm CMOS technology is presented in this paper. The double precharge TSPC DFF can reduce setup time compared with the conventional one, so it contributes to enhancing the operating speed of a dual-modulus prescaler. A 128/129 dual-modulus prescaler using the proposed flip-flop shows a maximum operating frequency of 3 GHz with 16 mW power consumption at 3.3 V power supply
Keywords :
CMOS digital integrated circuits; clocks; dividing circuits; flip-flops; frequency synthesizers; high-speed integrated circuits; prescalers; 0.35 micron; 16 mW; 3 GHz; 3.3 V; CMOS technology; double precharge TSPC; flip-flop; frequency synthesizers; high-speed dual-modulus prescaler; operating frequency; operating speed; power consumption; setup time; Application specific integrated circuits; CMOS technology; Clocks; Counting circuits; Delay effects; Energy consumption; Flip-flops; Frequency conversion; Frequency synthesizers; Logic;
Conference_Titel :
VLSI and CAD, 1999. ICVC '99. 6th International Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5727-2
DOI :
10.1109/ICVC.1999.821014
