Power efficient CAM using adiabatic logic

This paper presents a design of power efficient content addressable memory using energy recycling principle of adiabatic logic. The storage array is built by using basic 9T CAM cell but the decoders which drives the bitlines and wordlines are realized using two different adiabatic logic structures such as Complementary Pass Transistor Adiabatic Logic and Efficient Charge Recovery Adiabatic Logic. The wordlines, bitlines and matchlines are major source of power consumption, thus charges of node capacitances on these lines are well recovered. A comparison is made between the conventional CAM Architecture and CPAL, ECRL CAM Architectures. The simulation results of 4×4 adiabatic logic CAM proves to be better with a power saving of 40% than the conventional one. The circuits are designed using 180nm CMOS technology with power supply of 1.8V using Cadence Virtuoso.