A Fast JPEG2000 EBCOT Tier-1 Architecture That Preserves Coding Efficiency

Embedded block coding, EBCOT tier-1, is the most computationally intensive part of the JPEG2000 image coding standard. Past research on fast EBCOT tier-1 hardware implementations has concentrated on cycle efficient context formation. These pass-parallel architectures require that JPEG2000´s three mode switches be turned on; thus, coding efficiency is sacrificed for improved throughput. In this paper a new fast EBCOT tier-1 design is presented: it is called the split arithmetic encoder (SAE) process. The proposed process exploits concurrency to obtain improved throughput while preserving coding efficiency. The SAE process is evaluated using two methods: clock cycle estimation, and FPGA hardware implementation. Both methods achieve throughput improvement; the hardware implementation exhibits the largest speedup.