Title :
Designing Robust Asynchronous Circuits Based on FinFET Technology
Author :
Jafari, Fataneh ; Mosaffa, Mahdi ; Mohammadi, Siamak
Author_Institution :
Dependable Syst. Design Lab., Univ. of Tehran, Tehran, Iran
Abstract :
Double-gate FinFETs have proved to be a promising alternative for deep sub-micron bulk CMOS. In this paper, we have investigated the feasibility of FinFET transistors in asynchronous design which has gained much attention for its advantages such as absence of clock distribution, process variation aware performance, and robustness. Excellent short-channel characteristic, low leakage power, threshold voltage control and the potential of designing area-efficient circuits are the motivation to employ FinFET transistor in asynchronous circuit design. We have designed three novel FinFET-based asynchronous static C-elements which differ in front gate and back gate connections. They are evaluated in terms of leakage and dynamic power, area, and delay characteristics and compared against bulk CMOS C-element in 32nm technology. With technology scaling, vulnerability of combinational logic to soft errors exponentially increases. In this paper we also examine these C-elements nodes sensitivity against soft errors and propose a robust logic. We show that our proposed robustness method increases robustness of the most sensitive node in Shorted gate (SG) and Low power (LP) C-elements 60 times. A dual rail Muller pipeline has been designed with each kind to evaluate our C-elements and compare them to bulk MOSFET pipeline. Compared to SG, simulation results show that Independent gate (IG) and LP modes are most efficient in area and leakage power respectively and in terms of robustness SG and LP modes show better robustness than IG mode.
Keywords :
MOSFET; asynchronous circuits; combinational circuits; logic design; asynchronous static C-elements; back gate connections; clock distribution; combinational logic; deep sub-micron bulk CMOS; double-gate FinFET technology; dual rail Muller pipeline; dynamic power; front gate connections; independent gate; leakage power; process variation aware performance; robust asynchronous circuit design; size 32 nm; soft errors; technology scaling; threshold voltage control; Digital systems; C-element; Fin FET; leakage; power; robustness;
Conference_Titel :
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location :
Oulu
Print_ISBN :
978-1-4577-1048-3
DOI :
10.1109/DSD.2011.55