Title :
Low Power FPGA Implementations of JH and Fugue Hash Functions
Author :
Provelengios, George ; Voros, Nikolaos S. ; Kitsos, Paris
Author_Institution :
Dept. of Telecommun. Syst. & Networks, Technol. Educ. Inst. of Mesolonghi, Mesolonghi, Greece
Abstract :
Low power techniques in a FPGA implementation of the hash functions called JH and Fugue are presented in this paper. The JH hash function is under consideration for adoption as standard. Pipeline technique (with some variants) and the use of embedded RAM blocks are the techniques in order to reduce the power consumption. Power consumption reduction between 6.3% and 33 % was achieved for JH function and similar a power reduction between 1.7% and 13.3 % was achieved for Fugue by means of the proposed techniques compared with the implementation without any low power issue.
Keywords :
cryptography; field programmable gate arrays; low-power electronics; pipeline processing; random-access storage; Fugue hash function; JH hash function; embedded RAM blocks; low power FPGA; pipeline technique; power consumption reduction; Clocks; Field programmable gate arrays; Hardware; Logic gates; Pipelines; Random access memory; Registers; FPGA; VIRTEX-5; hash functions; low power techniques;
Conference_Titel :
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location :
Oulu
Print_ISBN :
978-1-4577-1048-3
DOI :
10.1109/DSD.2011.56
