DocumentCode
1579117
Title
Synthesizing Concurrent Synchronous Computing Machines from Interrupt-Driven Binaries
Author
Wilder, Michael D. ; Rinker, Robert E.
Author_Institution
Univ. of Idaho, Idaho Falls, ID, USA
fYear
2011
Firstpage
430
Lastpage
433
Abstract
Soft processors are increasingly being used to host embedded systems applications on reconfigurable computing platforms such as the field-programmable gate array (FPGA). Soft processors are sequential, synchronous devices that are not capable of exploiting the concurrency available on FPGAs. We present a method for automatically synthesizing interrupt-driven binaries into custom, self-contained, circuitizable finite-state machine with data path (FSMD) descriptions that are capable of leveraging the concurrency of the FPGA. We show how this method increases the computational density of interrupt-driven applications while decreasing interrupt servicing latencies, mitigating live lock, and eliminating overhead associated with interrupt context switching. We discuss implications and limitations of this method, and describe a prototype which implements the method for programs targeted for the Intel 8051.
Keywords
field programmable gate arrays; finite state machines; hardware-software codesign; program compilers; reconfigurable architectures; Intel 8051; circuitizable finite state machine; concurrent synchronous computing machine; datapath description; field-programmable gate array; host embedded system application; interrupt driven binary; interrupt servicing latency; reconflgurable computing; soft processor; Arrays; Concurrent computing; Context; Field programmable gate arrays; Instruction sets; Message systems; automatic synthesis; binary synthesis; binary translation; compiler; embedded systems; hardware-software codesign;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location
Oulu
Print_ISBN
978-1-4577-1048-3
Type
conf
DOI
10.1109/DSD.2011.59
Filename
6037443
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