Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion

The diminished-one representation has been proposed for RNS-based systems with moduli of the 2ⁿ+1 forms as an encoding that is more efficient than the normal representation in the arithmetic processing units. However, its use necessitates a two-step reverse conversion, in which a diminished-to-normal conversion is first performed before the final residue-to-binary conversion resulting in performance loss. In this paper we introduce efficient modulo 2ⁿ+1 adders, sub tractors and multipliers that accept diminished-one operands at their inputs and derive normal operands at their outputs, that is, we embed the diminished-to-normal conversion within the arithmetic processing. Experimental results show that the proposed one-step approach is more efficient in terms of delay.