Title :
Efficient Fault Simulation of SystemC Designs
Author :
Lu, Weiyun ; Radetzki, Martin
Author_Institution :
ITI, Stuttgart Univ., Stuttgart, Germany
Abstract :
In this paper we present extensions to the SystemC library and automatable model transformations that enable efficient system-level fault simulation in SystemC. The method is based on extended data types which represent variables or signals as lists of values (instead of one value) consisting of a fault free reference value and any number of faulty values each of which corresponds to one fault. Faults (variable level faults as well as bit level faults) are injected to objects declared with the extended data types and are then propagated to other variables or SystemC channels during SystemC simulation, until either they are classified and dropped or the simulation ends. This work enables concurrent simulation of many faults in one SystemC simulation run. Two case studies exhibit a speedup up to 9 and 665 for permanent and transient variable level faults.
Keywords :
concurrency control; fault simulation; logic design; simulation languages; SystemC channels; SystemC designs; SystemC library; SystemC simulation; automatable model transformations; bit level faults; concurrent simulation; extended data types; fault free reference value; faulty values; permanent variable level faults; system-level fault simulation; transient variable level faults; Data models; Kernel; Mathematical model; Measurement; Switches; Transient analysis; SystemC; concurrent and comparative simulation; fault simulation; robustness;
Conference_Titel :
Digital System Design (DSD), 2011 14th Euromicro Conference on
Conference_Location :
Oulu
Print_ISBN :
978-1-4577-1048-3
DOI :
10.1109/DSD.2011.68