Analysis of dynamic comparators in ultra-low supply voltages for high speed ADCs

The need for ultra-low power and area efficient analog -to- digital converters (ADCs) is pushing towards the use of low voltage CMOS dynamic comparators to maximize the power efficiency and speed. The conventional dynamic comparators have features like high input impedance, no static power dissipation and good robustness against noise and mismatch. The drawback is that large numbers of transistors are used to minimize the offset, so the speed of the comparator is degraded. Double tail comparators overcome the drawbacks in conventional comparator by reducing the stacking of transistors with low supply voltage with less delay. But the transconductance is low for this comparator. In low power double tail comparator, without complicating the design and by adding few transistors the positive feedback in the regeneration is strengthened with results in reduced delay time. In this paper delay analysis of different dynamic comparators are presented with respect to speed and supply voltage. Then based on the delay analysis results, the conventional dynamic comparator is modified in terms of transistor technology and architecture results as body driven comparator for fast operation even in ultra low supply voltages. Simulation results in 90nm CMOS technology reveals that the delay time is considerably reduced.