An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating

Reducing energy consumption is a crucial for the embedded system design, and especially the leakage energy reduction is now big problem for the low power design. In order to reduce the leakage energy at standby time, power gating scheme is well known as a promising technique to realize partial power shutdown. However, the power gating usually causes penalties for shutdown and wakeup time, and this brings tradeoff between leakage energy reduction and latency penalty. This paper proposes energy aware design space exploration for power gated VLIW AGU model with fine grained power management. Contribution of this paper is an energy aware design space exploration with fast scheduling exploration for power gated VLIW AGU model. Experimental results show that proposed method can realize low power scheduling considering fine grained power management, and proposed architecture exploration method enables optimal design space exploration in practical time.