Title :
A multi-FPGA prototype of a DS1/HDSL synchronizer and desynchronizer prior to ASIC fabrication
Author :
Kelly, Daniel P. ; Hartmann, Quesnell J. ; Gude, Walter H.
Author_Institution :
Tellabs Operations, Inc., Lisle, IL, USA
Abstract :
As the speed and complexity of today´s ASICs continues to grow, conventional prototyping techniques for algorithm verification begin to break down. A novel implementation of DS1/HDSL synchronizer and desynchronizer utilizing an array of four FPGA devices to verify algorithm performances prior to ASIC fabrication is described. The utilization of FPGA devices for ASIC prototyping can significantly reduce the risk, cost, and time-to-market involved with complex ASIC devices
Keywords :
VLSI; application specific integrated circuits; field programmable gate arrays; flowcharting; hardware description languages; high level synthesis; logic CAD; programmable logic arrays; subscriber loops; synchronisation; ASIC prototyping; DS1/HDSL synchronizer; VHDL; VLSI; algorithm performances; compiled datapath circuits; cost; desynchronizer; fuse generation; high-bit-rate digital subscriber line; multi-FPGA prototype; risk; time-to-market; timing analysis; Application specific integrated circuits; Costs; DSL; Fabrication; Field programmable gate arrays; Frequency synchronization; Jitter; Prototypes; Testing; Timing;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410732
