Title :
Planarization yield limiters for wafer-scale 3D ICs
Author :
Gupta, M. ; Rajagopalan, G. ; Hong, C.K. ; Lu, J.-Q. ; Rose, K. ; Gutmann, R.J.
Author_Institution :
Center for Microcontamination Control, Rensselaer Polytech. Inst., Troy, NY, USA
fDate :
6/24/1905 12:00:00 AM
Abstract :
The planarization requirements for 3D processing are compared to those for conventional 2D processing, indicating that wafer level planarity is essential for 3D as compared to the die level planarity needed for 2D ICs. A yield test structure has been designed to study the number of electrical faults that occur during damascene patterning. Initial experimental data with this test vehicle show that planarity changes with pattern density, although the functional relationship has not been established to date.
Keywords :
chemical mechanical polishing; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; integrated circuit yield; wafer bonding; wafer-scale integration; CMP; Cu; chemical-mechanical planarization; damascene patterning; electrical faults; global planarity; pattern density; planarization yield limiters; wafer level planarity; wafer-scale 3D ICs; yield test structure; Circuit testing; Copper; Delay; Dielectric materials; Integrated circuit interconnections; Optical materials; Planarization; Thin film transistors; Wafer bonding; Wires;
Conference_Titel :
Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop
Print_ISBN :
0-7803-7158-5
DOI :
10.1109/ASMC.2002.1001618
