Title :
RF FET layout and modeling for design success in RFCMOS technologies
Author :
Jagannathan, B. ; Greenberg, D. ; Anna, R. ; Wang, X. ; Pekarik, J. ; Breitwisch, M. ; Erturk, M. ; Wagner, L. ; Schnabel, C. ; Sanderson, D. ; Csutak, S.
Author_Institution :
SRDC, IBM Microelectron., USA
Abstract :
This paper presents challenges in creating high quality RF FET layouts and models in CMOS technologies spanning 0.25 μm to 90 nm nodes. The focus is on developing a comprehensive methodology to provide robust, high performance parameterized RF FET layout cells and corresponding scalable RF models to enable RF designs that fully leverage the cost benefit potential of CMOS technology.
Keywords :
CMOS integrated circuits; MOSFET; radiofrequency integrated circuits; semiconductor device models; semiconductor device noise; 0.25 micron to 90 nm; CMOS; RF FET modeling; RFCMOS technologies; de-embedding; noise models; parameterized FET layout cells; scalable RF models; CMOS technology; FETs; Inductors; Isolation technology; Paper technology; Radio frequency; Resistors; Semiconductor device modeling; Silicon; Varactors;
Conference_Titel :
Radio Frequency integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE
Print_ISBN :
0-7803-8983-2
DOI :
10.1109/RFIC.2005.1489495
