DocumentCode
1580218
Title
Design methodologies of comparators based on parallel hardware algorithms
Author
FURUYA, KIYOSHI
Author_Institution
Chuo Univ., Tokyo, Japan
fYear
2010
Firstpage
591
Lastpage
596
Abstract
Various comparator designs that are suitable for current device technology are shown. The designs are based on LSB-first or MSB-first approaches. Linear operation time designs are derived as the first step. O(log n) operations time with O(n) or O(n log n) hardware cost are attained by parallel implementation of prefix operations and reductions.
Keywords
comparators (circuits); computational complexity; logic design; LSB-first approach; MSB-first approach; comparator design; linear operation time design; parallel hardware algorithm; Algorithm design and analysis; Binary trees; Delay; Hardware; Logic gates; Parallel algorithms; Semiconductor devices; digital comparator; parallel hardware algorithm; prefix operation; reduction;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Information Technologies (ISCIT), 2010 International Symposium on
Conference_Location
Tokyo
Print_ISBN
978-1-4244-7007-5
Electronic_ISBN
978-1-4244-7009-9
Type
conf
DOI
10.1109/ISCIT.2010.5665060
Filename
5665060
Link To Document