DocumentCode :
1580659
Title :
METRO-3D: an efficient three-dimensional wafer inspection simulator for next generation lithography
Author :
Zhu, Zhengrong ; Swecker, Aaron L. ; Strojwas, Andrzej J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Firstpage :
396
Lastpage :
401
Abstract :
Wafer inspection schemes for next generation lithography (NGL) will play a key role in controlling defect mechanisms and maintaining an acceptable yield. Developing these wafer inspection schemes will require characterization and optimization of DUV wavelength illumination at high numerical apertures (greater than 0.9) to detect defects that may be a fraction of the design rule. Using wafer inspection test benches that provide the flexibility for various illumination polarizations, numerical apertures, scanning or full field schemes can be extremely costly and therefore simulation of these schemes is necessary to characterize the various detection parameters. To model defects for NGL, three-dimensional simulation tools will be required to simulate highly absorptive material in the environment of shorter wavelength illumination. Also, the simulator will be required to simulate high numerical aperture (NA) inspection schemes to capture small defects. With the development of METRO-3D, a three-dimensional simulation tool that rigorously solves the EM field on arbitrary wafer topographies, we are able to model and characterize the wafer inspection schemes for NGL. In this paper, we will present simulation results from METRO-3D for various wafer inspection schemes, including high numerical aperture schemes, on NGL topographies with highly absorptive materials.
Keywords :
inspection; semiconductor process modelling; ultraviolet lithography; DUV lithography; EM field; METRO-3D simulation; absorptive material; defect detection; next generation lithography; numerical aperture; surface topography; three-dimensional wafer inspection; Apertures; Design optimization; Inspection; Lighting; Lithography; Numerical simulation; Polarization; Semiconductor device modeling; Surfaces; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop
Print_ISBN :
0-7803-7158-5
Type :
conf
DOI :
10.1109/ASMC.2002.1001640
Filename :
1001640
Link To Document :
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