Design and implementation of High Performance Visual Stimulator for Brain Computer Interfaces

Author

Jaganathan, V. ; Mukesh, Srihari M T ; Reddy, Ramasubba M.

Author_Institution

Dept. of Appl. Mech., Indian Inst. of Technol., Chennai

fYear

2006

Firstpage

5381

Lastpage

5383

Abstract

An algorithm for implementing visual stimulators on generic computers has been developed for brain computer interfaces (BCIs). It uses the hardware counter present in these systems to derive accurate timing. Simultaneous display of 20 patterns (e.g. 3times3 checkerboards) modulated at different frequencies is possible. The pattern used for stimulating the steady state visual evoked potential (SSVEP) can be changed with ease. The stimulators are evaluated using software counters. High accuracy (less than 0.73% error) and precision (0.1% coefficient of variation) is recorded for 20 patterns set with frequencies between 6 Hz and 15 Hz

Keywords

brain; handicapped aids; visual evoked potentials; 6 to 15 Hz; BCI; SSVEP; brain computer interfaces; high performance visual stimulator; steady state visual evoked potential; Biomedical engineering; Brain computer interfaces; Computer errors; Counting circuits; Electroencephalography; Frequency modulation; Hardware; Light emitting diodes; Steady-state; Timing; Brain-computer interface (BCI); steady state visual evoked potential (SSVEP); visual stimulator;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering in Medicine and Biology Society, 2005. IEEE-EMBS 2005. 27th Annual International Conference of the

Conference_Location

Shanghai

Print_ISBN

0-7803-8741-4

Type

conf

DOI

10.1109/IEMBS.2005.1615698

Filename

1615698