Title :
Design of an analog CMOS self-learning MLP chip
Author :
Bo, G.M. ; Caviglia, D.D. ; Chiblè, H. ; Valle, M.
Author_Institution :
Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
Abstract :
In this paper we present the analog CMOS design of a multi-layer-perceptron network with on-chip by-pattern back-propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient in terms of convergence speed. Circuit simulation results validate the network behavior
Keywords :
CMOS analogue integrated circuits; analogue processing circuits; backpropagation; convergence; multilayer perceptrons; neural chips; unsupervised learning; 0.7 micron; 25 mW; analog CMOS chip design; convergence speed; learning algorithm; local learning rate adaptation technique; multi-layer-perceptron network; onchip by-pattern backpropagation learning; self-learning MLP chip; Artificial neural networks; Circuit simulation; Computer architecture; Computer networks; Convergence; Design engineering; Electronic mail; Network-on-a-chip; System-on-a-chip; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.703893
