DocumentCode
1581519
Title
Two-stage high gain low power OpAmp with current buffer compensation
Author
Rajput, Sudheesh K. ; Hemant, B.K.
Author_Institution
Dept. of ECE, Amity Univ., Noida, India
fYear
2013
Firstpage
121
Lastpage
124
Abstract
This paper presents the classic two stage CMOS opamp design by employing the current buffer compensation strategy. The designed low power opamp produces an open loop gain above 78 dB, an improved gain-bandwidth product (GBW) 5.82 MHz with an adequate pahse margin of 63.9° in 0.35 μm CMOS technology. The circuit is operated at the single supply voltage of 3.3V with power dissipation of 144.3 μW and an enhanced offset voltage of only 61.5 μV compare to 318 μV offset in [7].
Keywords
CMOS integrated circuits; buffer circuits; integrated circuit design; mixed analogue-digital integrated circuits; operational amplifiers; CMOS opamp design; CMOS technology; bandwidth 5.82 MHz; current buffer compensation; gain bandwidth product; power 144.3 muW; size 0.35 mum; two stage high gain low power opamp; voltage 3.3 V; voltage 318 muV; voltage 61.5 muV; Bandwidth; CMOS integrated circuits; Circuit stability; Educational institutions; Gain; MOS devices; Stability analysis; CMOS; current buffer; low power; opamp;
fLanguage
English
Publisher
ieee
Conference_Titel
Global High Tech Congress on Electronics (GHTCE), 2013 IEEE
Conference_Location
Shenzhen
Type
conf
DOI
10.1109/GHTCE.2013.6767255
Filename
6767255
Link To Document