Impact of PWM jitter to switching-mode power converter efficiency

This paper proposes a methodology to demonstrate the impact of the Pulse-Width-Modulation (PWM) jitter effect to the power conversion efficiency of switching power converters. First, the origin of PWM jitter is introduced. The power-loss equivalent circuit model with corresponding equations are developed to understand the mechanism of power losses. Both computer simulation and hardware circuit are established to verify the impact of the PWM jitter to the conversion efficiency. An external sinusoidal perturbation signal with variable frequency is induced to the voltage control loop to produce a controllable PWM jitter in order to observe the change of power converter efficiency. The validity of the proposed methodology is verified by the simulated and the measured results.