Solid-state modulator R&D for JLC

The klystron modulator for the Japan Linear Collider (JLC) is required to produce a 500 kV, 530 A, 1.5 /spl mu/s flat-top pulse, and to drive a pair of 75 MW PPM-klystrons. To improve the reliability and energy efficiency, we are developing a solid-state modulator with a 1:5 primary split pulse transformer. This modulator consists of two parallel modulator units, each driving the primary winding of the transformer. Each modulator unit uses multiple pulse modulators stacked in series, and generates a 50 kV pulse at 2650 A. This allows fast over-current protection and easy-to-control flat-top tuning of the output waveform. In our present study, a ten-stage test modulator has been built and has been successfully operated at 20 kV and switched up to 2890 A peak. It was also confirmed that this modulator enables us to produce excellent output waveform with a wide flat-top and it improves the power efficiency.