Design of a 5-bit, 4.87GS/s, 240µW Flash ADC using a MUX-based decoder with Regenerative Buffer in 45-nm CMOS

Author

Bharathesh Patel, N. ; Muralidhara, K.N.

Author_Institution

Dept. of Electr. & Electron. Eng., G. Madegowda Inst. Technol., Mandya, India

fYear

2015

Firstpage

1

Lastpage

7

Abstract

This paper presents a 5 - bit 4.87GSps Flash ADC design using 45-nm GPDK CMOS technology library. The designed system consists of two main blocks as comparator array and digital decoder. The digital decoder contains 2:1 MUX based 1 - of - N decoder and Regenerative Buffer units. As a result, active die area and the power consumption are reduced in addition to increase in sampling frequency. The power supply voltage range for the overall system is ± 1.8V. The simulation results include maximum power consumption of 0.24 mW. The Conversion time 204p sec, the measured DNL and INL to less than 0.02LSB and 0.1LSB.

Keywords

CMOS integrated circuits; analogue-digital conversion; decoding; integrated circuit design; low-power electronics; GPDK CMOS technology; active die area; comparator array; digital decoder; flash ADC; multiplexing based decoder; power 240 muW; power consumption; regenerative buffer units; size 45 nm; voltage 1.8 V; CMOS integrated circuits; Conferences; Decoding; Layout; Multiplexing; Resistors; Transistors; CMOS VLSI; Flash ADC; GPDK CMOS; High Speed Data Converters;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovations in Information, Embedded and Communication Systems (ICIIECS), 2015 International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-6817-6

Type

conf

DOI

10.1109/ICIIECS.2015.7193230

Filename

7193230