Optimization of quarter micron MOSFETs for low voltage/low power applications

A case study of MOSFET technology optimization for low voltage (1 V), low power applications is presented. Technology parameters (threshold voltage, oxide thickness) were optimized for power and speed with the consideration of balancing switching power and static power dissipation and the impact of process/ambient variation. Well and substrate ties were separated from supply rails and controlled separately to compensate for process and ambient variations. For the same switching speed, fabricated devices show a 4.5× reduction in switching power when compared with standard devices operated at a higher supply voltage. An implementation of a self tuning system using the low/tunable threshold device in a VLSI environment is presented