Title :
Intra-die device parameter variations and their impact on digital CMOS gates at low supply voltages
Author :
Eisele, M. ; Berthold, J. ; Thewes, R. ; Wohlrab, E. ; Schmitt-Landsiedel, D. ; Weber, W.
Author_Institution :
R&D, Siemens AG, Munich, Germany
Abstract :
Statistical intra-die variations of device parameters from a 0.5 μm CMOS process are determined, finding good agreement with the (WL) -1/2 model. It is proven that channel doping variations are responsible. Additionally, systematic proximity-induced parameter deviations due to different field oxide surroundings are found. The resulting variations of inverter delays for different supply voltages and gate areas are determined
Keywords :
CMOS digital integrated circuits; MOSFET; characteristics measurement; delays; integrated circuit measurement; integrated circuit testing; logic gates; statistical analysis; (WL)-1/2 model; 0.5 mum; channel doping variations; chip measurements; digital CMOS gates; field oxide surroundings; intra-die device parameter variations; inverter delays; low supply voltages; n-MOSFETs; output characteristics; p-MOSFETs; proximity-induced parameter deviations; statistical intra-die variations; CMOS process; Capacitance; Current measurement; Delay; Inverters; Low voltage; MOSFET circuits; Research and development; Testing; Voltmeters;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.497184
