Underfill Assessments and Validations for Low-k FCBGA

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os and better electrical characteristics under same package form factor. Flip chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the concerns of reliability of low-k material integrated into IC chip. The typical failure modes are dielectric layers delamination and crack under temperature loading during assembly or reliability test. Thus, the adequate underfill material selection becomes very critical to protect low-k dies. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent from failures on bump and low-k chip. Firstly, test vehicle in this study was a FCBGA package with heat spreader and was investigated by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for several underfill characterizations. Finally, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests