An analog discrete-time transversal filter in 2.0 μm CMOS

The implementation of analog discrete-time transversal filters using track-and-holds (T/Hs) as delay elements is addressed. With a classic linear tapped-delay line topology, the sampling rate is typically limited by the acquisition time of the T/Hs. To overcome this limitation, a circular architecture has been developed. The chip presented is the first demonstration of the circular architecture. A four-tap equalizer has been fabricated in a 2-μm CMOS process, dissipates 148 mW when running at 30 MHz, and has a total area of 4.8 mm ²