• DocumentCode
    1584072
  • Title

    Ball Impact Responses of Wafer-level Chip-scale Packages

  • Author

    Lai, Yi-Shao ; Chang, Hsiao-Chuan ; Yeh, Chang-Lin

  • Author_Institution
    Lab. of Stress-Reliability, Advanced Semicond. Eng., Inc.
  • fYear
    2006
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    The ball impact test (BIT) was developed based on the demand of a package-level measure of the board-level reliability of solder joints in the sense that it leads to brittle intermetallic fracturing, similar to that from a board-level drop test. The BIT itself stands alone as a unique and novel test methodology in characterizing strengths of solder joints under a high-speed shearing load. In this work, we present BIT results conducted on package-level 95.5Sn-4Ag-0.5Cu solder joints of a wafer-level chip-scale package, under an impact velocity of 1.4 m/s. Scanning electron microscopy was also performed to investigate morphologies around under bump metallurgy (UBM) before and after BIT
  • Keywords
    brittle fracture; chip scale packaging; copper alloys; fracture toughness testing; impact (mechanical); integrated circuit reliability; integrated circuit testing; silver alloys; solders; tin alloys; wafer level packaging; 1.4 m/s; 95.5Sn-4Ag-0.5Cu solder joints; SnAgCu; ball impact test; board-level reliability; brittle intermetallic fracturing; high-speed shearing load; scanning electron microscopy; under bump metallurgy; wafer-level chip-scale packages; Chip scale packaging; Intermetallic; Lead; Morphology; Scanning electron microscopy; Semiconductor device measurement; Shearing; Soldering; Testing; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly Conference Taiwan, 2006. IMPACT 2006. International
  • Conference_Location
    Taipei
  • Print_ISBN
    1-4244-0735-4
  • Electronic_ISBN
    1-4244-0735-4
  • Type

    conf

  • DOI
    10.1109/IMPACT.2006.312206
  • Filename
    4107463