Title :
Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP
Author :
Yew, Ming-Chih ; Chang, Shu-Ming ; Chiang, Kuo-Ning
Author_Institution :
Lab. of Adv. Microsyst. Packaging & Nano-Mechanics Res., Nat. Tsing Hua Univ., Hsinchu
Abstract :
The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) causes a reliability issue for the ball grid array type electronic package. This makes it difficult for the conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirement. Therefore, in this study a novel solder joint protection-WLCSP (SJP-WLCSP) structure is proposed to overcome the reliability issue. The SJP-WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP-WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer. To elucidate the thermo-mechanical behavior of eutectic solder joints and copper trace, a nonlinear analysis based on the 3D finite element (FE) model under accelerated thermal test loadings was carried out. The crack of the SJP-WLCSP test vehicle after thermal cycling loadings exhibits a good agreement between the failure analysis experiments and the FE method predictions
Keywords :
ball grid arrays; chip scale packaging; copper; cracks; delamination; failure (mechanical); finite element analysis; printed circuits; protection; reliability; solders; thermal expansion; wafer level packaging; 3D finite element model; PCB; WLCSP; accelerated thermal test; ball grid array; coefficient of thermal expansion; copper trace; cracks; delaminating layer; electronic package; eutectic solder joints; failure analysis; insulating layer; organic printed circuit board; redistribution copper metal traces; reliability analysis; reliability issue; soft joint protection technology; thermal cycling loadings; thermo-mechanical behavior; wafer level chip scaled packaging; Copper; Electronic packaging thermal management; Printed circuits; Protection; Silicon; Soldering; Testing; Thermal expansion; Thermal loading; Wafer scale integration;
Conference_Titel :
Microsystems, Packaging, Assembly Conference Taiwan, 2006. IMPACT 2006. International
Conference_Location :
Taipei
Print_ISBN :
1-4244-0735-4
Electronic_ISBN :
1-4244-0735-4
DOI :
10.1109/IMPACT.2006.312212