Title :
Development of neural network tools for ASIC design
Author :
Gassen, David W. ; Carothers, Jo Dale
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona, Univ., Tucson, AZ, USA
Abstract :
The scheduling and allocation phase is a critical phase in the high-level behavioral synthesis of ASICs. A neural network model is presented which schedules a dataflow graph under several simultaneous constraints: a limited number of control steps, buses, and hardware units, and an objective to minimize data path lengths. Comparisons with such heuristic approaches as ALAP demonstrate typically superior solutions
Keywords :
Hopfield neural nets; circuit layout CAD; circuit optimisation; data flow graphs; high level synthesis; integrated circuit layout; scheduling; wave digital filters; ASIC design; Hopfield network; data path length minimisation; dataflow graph; high-level behavioral synthesis; neural algorithms; neural network tools; simultaneous constraints; wave filter; Application specific integrated circuits; Artificial neural networks; Design engineering; Network synthesis; Neural network hardware; Neural networks; Optimal scheduling; Optimization methods; Process design; Processor scheduling;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410747
