• DocumentCode
    1584323
  • Title

    A technique for designing bidirectional error-free combinational logic circuits

  • Author

    Busaba, Fadi Y. ; Lala, Parag K.

  • Author_Institution
    Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
  • fYear
    1992
  • Firstpage
    903
  • Abstract
    A technique is presented for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit errors at the output. Once the outputs of a circuit are encoded, unconstrained multilevel optimization can be applied to the circuit. An algorithm that detects whether a fault at an input line might result in bidirectional errors at the output is given. An algorithm for building circuits such that any stuck-at fault at an input line will result in unidirectional errors at the outputs is also proposed
  • Keywords
    combinatorial circuits; logic design; optimisation; bidirectional error-free combinational logic circuits; single bit error; single stuck-at fault; unconstrained multilevel optimization; unidirectional multibit errors; Automatic testing; Buildings; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Encoding; Fault detection; Monitoring; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
  • Conference_Location
    Pacific Grove, CA
  • ISSN
    1058-6393
  • Print_ISBN
    0-8186-3160-0
  • Type

    conf

  • DOI
    10.1109/ACSSC.1992.269089
  • Filename
    269089