DSP-based clock recovery implemented in a field programmable gate array

In data communication systems, a clock signal is normally extracted from the received data so that the data can be properly decoded. The baseband coding scheme may be chosen so that the data contains a strong spectral component at the desired clock rate. Such codes are termed “self clocking”. A phase locked loop (PLL) may be used to recover the clock signal from the data, but loss of lock and synchronisation can occur if the data “fades” for a period of time. Problems can also occur in regaining lock if the received data are poor and this results in lost data. Also, in order to ensure that the PLL is in a locked condition before data are received a long synchronising sequence must be applied before the data can be accurately clocked. A DSP clock recovery scheme exploits the feature of a long impulse response in an IIR (infinite impulse response) filter, when the poles are close to the unit circle. In the context of clock recovery this feature is desirable since it can be exploited to provide a good flywheel effect over periods of lost input, i.e. a fade