Title :
A synthesis tool based design of a 111 MHz CMOS floating point adder with built in testability
Author :
Fernandes, Denzil ; Raj, Vijay ; Doriswamy, Narsimhan ; Dorenbosch, J. ; Bowden, Mark ; Kapoor, Vishal S.
Author_Institution :
Comput. Sci. Eng., Texas, Univ., Arlington, TX, USA
Abstract :
A floating point adder was designed which operates at 111 MHz. The design was done using OASIS. OASIS is a standard cell based logic synthesis system with automatic test vector generation capability. The resulting layout is smaller than a corresponding custom chip despite the additional test circuitry in the OASIS based design
Keywords :
CMOS logic circuits; adders; application specific integrated circuits; automatic test software; built-in self test; circuit layout CAD; floating point arithmetic; high level synthesis; integrated circuit layout; logic testing; 111 MHz; ASIC; CMOS floating point adder; OASIS; automatic test vector generation capability; built in testability; high level synthesis tools; logic synthesis system; standard cell based; synthesis tool based design; Adders; Circuit synthesis; Circuit testing; Clocks; Computer science; Logic testing; Pipelines; Superconducting filters; Superconducting logic circuits; System testing;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410749
