Interconnect optimization in behavioral synthesis of ASICs

A new quadratic time global interconnect allocation algorithm for ASIC data path synthesis is presented. The algorithm is based on graph coloring and flipping commutative operation inputs and it has two phases: phase one sets an upper bound on number of multiplexer/bus inputs while phase two minimizes multiplexer/bus inputs as well as the number of two-input multiplexer equivalent of the interconnection network using interconnect merging techniques. The algorithm was applied to problems taken from current literature, and the results compare favorably to those for previous techniques