ECL I/O buffers for BiCMOS integrated systems: A tutorial overview

Author

Pickles, Neil S. ; Lefebvre, Martin C.

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada

fYear

1993

Firstpage

436

Lastpage

443

Abstract

The authors describe the methodology for the design and layout of fast BiCMOS ECL I/O buffers. Principles of ECL circuit operation are described with emphasis on the NOR/OR gate and the bandgap voltage reference. A comparison of ECL 10 K and 100 K logic families is presented as well as complete designs for an input and output buffer. The pad macros are temperature and supply voltage compensated and have nominal rise and fall times of 400 ps

Keywords

BiCMOS digital integrated circuits; BiCMOS logic circuits; SPICE; application specific integrated circuits; buffer circuits; circuit layout CAD; emitter-coupled logic; integrated circuit layout; logic CAD; very high speed integrated circuits; 400 ps; ASIC; BiCMOS integrated systems; ECL I/O buffers; NOR/OR gate; SPICE; bandgap voltage reference; design; fall times; high-speed circuit simulation; layout; pad macros; rise times; supply voltage compensated; temperature compensated; tutorial; BiCMOS integrated circuits; Circuit noise; Design methodology; Logic circuits; Logic design; Photonic band gap; Power supplies; Temperature; Tutorial; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410754

Filename

410754