Three volt to five volt CMOS interface circuit device leakage limited DC power dissipation

A CMOS interface circuit from three to five volts is presented in which DC power consumption is defined by a single transistor´s OFF leakage current. The interface design provides signal level translation while minimizing propagation delay and power dissipation. Typical propagation delays are on the order of 1.5 ns, with DC power dissipation less than 1 pW. The primary application of the interface is mixed voltage gate arrays with a 3.3-V core and 5.0-V I/Os