DocumentCode
1584760
Title
New multiplier design based on squared law algorithms and table look-ups
Author
Rao, Poomachandra B. ; Skavantzos, Alexander
Author_Institution
Louisiana State Univ., LA, USA
fYear
1992
Firstpage
686
Abstract
A multiplier design based on look-up tables and squared law algorithms is presented. This multiplier can compute the full precision product of two integer numbers or their product modulo 2N, modulo 2N-1, or modulo 2N+1. The design is based on decomposing the two numbers into smaller sizes, performing the cyclic convolution on these smaller numbers, and then finally reconstructing the desired product. The algorithms use no multiplications and instead rely only on squaring operations, additions, and subtractions. A comparative analysis of ROM requirements and hardware complexities for performing the multiplication operation using various look-up techniques is presented
Keywords
digital arithmetic; multiplying circuits; table lookup; ROM; additions; cyclic convolution; hardware complexities; squared law algorithms; squaring operations; subtractions; table look-ups; Algorithm design and analysis; Computer architecture; Concurrent computing; Equations; Hardware; Read only memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on
Conference_Location
Pacific Grove, CA
ISSN
1058-6393
Print_ISBN
0-8186-3160-0
Type
conf
DOI
10.1109/ACSSC.1992.269108
Filename
269108
Link To Document