Title :
Digital transistor sizing techniques applied to 100K ECL CMOS output buffers
Author :
Gabara, Thaddeus J. ; Fischer, Wilhelm
Author_Institution :
AT&T Bell Lab. Murray Hill, NJ, USA
Abstract :
Regulated current levels have been maintained with a control circuit that digitally adjusts the effective width of a 0.9-μm CMOS output buffer to generate 100 K ECL levels operating up to 800 MHz. A pseudo-random bit error rate test of the buffer operating at 1.6 Gb/s indicated no errors Digital sizing reduces the variation of internal power dissipation over operating conditions from 250% to 10%
Keywords :
CMOS logic circuits; application specific integrated circuits; buffer circuits; driver circuits; emitter-coupled logic; logic arrays; very high speed integrated circuits; 1.6 Gbit/s; 800 MHz; ASIC; ECL CMOS output buffers; VLSI; array partitioning; control circuit; digital transistor sizing techniques; net glitch impulse area; pseudo-random bit error rate test; CMOS digital integrated circuits; Circuit testing; Distributed parameter circuits; Driver circuits; Frequency; Power dissipation; Power transmission lines; Signal generators; Variable structure systems; Voltage control;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410758
