Title :
Characteristics of full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material
Author :
Malhi, Satwinder ; Anderson, McRay ; Shen, C.C. ; Bean, Ken ; Sundaresan, Ravi ; Gopffarth, Greg ; Lindberg, Keith ; Yeakley, Dick ; Smith, Jerry
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
Summary form only given. A full etchstop layer transfer/silicon-on-insulator (FELT/SOI) material process has been developed that meets the following criteria: (1) the material quality is identical to epitaxial silicon layers; (2) the SOI layer thickness is well controlled; (3) the insulator material choice and thickness is variable; (4) the device-to-device isolation is left to customer discretion. In the FELT/SOI process, a p+ etchstop layer is fabricated on a lightly doped starting substrate followed by epitaxial layer deposition with the type and resistivity required for the final SOI layer. Next an insulator layer is either grown or deposited followed by thick polysilicon deposition as is typical in standard DI process. The original substrate is now mechanically ground up to the vicinity of p+ etchstop layer. The remaining silicon overlying the etchstop layer and the etchstop layer itself are then removed in doping sensitive etches followed by surface finish. The SOI layer thickness control over a nominally 10-μm layer on a 4-in wafer is ±0.5 μm, and the layer shows no material defects. Bipolar transistors fabricated on this material and epitaxial control material show comparable performance in terms of high gain sharp junction breakdown, and good yield
Keywords :
bipolar integrated circuits; elemental semiconductors; integrated circuit technology; semiconductor technology; silicon; 10 micron; 4 in; DI process; SOI; SOI layer thickness; SOI layer thickness control; Si on insulation; Si-SiO2; bipolar transistors; criteria; device-to-device isolation; dielectric isolation process; full etchstop layer transfer; gain; insulator material choice; junction breakdown; material quality; yield; Bipolar transistors; Conductivity; Doping; Epitaxial layers; Etching; Insulation; Silicon on insulator technology; Substrates; Surface finishing; Thickness control;
Conference_Titel :
SOS/SOI Technology Workshop, 1988. Proceedings., 1988 IEEE
Conference_Location :
St. Simons Island, GA
DOI :
10.1109/SOI.1988.95396