Design of a high speed interface for 0.5μm gate arrays

Author

Ramsay, Frank R.

Author_Institution

Toshiba American Electronics Components, Inc., San Jose, CA, USA

fYear

1993

Firstpage

468

Lastpage

471

Abstract

Modern systems running at clock rates of 50-150 MHz need high-performance interfaces for use between different logic and memory chips on the PCB. There is also a need for very tight clock skew control. The author examines the requirements of high-performance input/output buffers (I/Os) and clock skew control for 0.5-μm gate arrays. In order to produce a cost-effective and performance-optimized I/O, it is sometimes necessary to use embedded I/O constructions. These are where the I/O structures are customized for a given application from a series of predesigned options

Keywords

application specific integrated circuits; buffer circuits; cellular arrays; logic arrays; modules; phase locked loops; system buses; very high speed integrated circuits; 0.5 micron; 50 to 150 MHz; analog PLL; clock skew control; cost-effective; customized; embedded I/O constructions; gate arrays; high speed interface; high-performance; input/output buffers; masterslice; predesigned options; Application specific integrated circuits; Bonding; Clocks; Cost function; Electronic components; Libraries; Logic; Packaging; Random access memory; Reflection;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-1375-5

Type

conf

DOI

10.1109/ASIC.1993.410761

Filename

410761