Modelling Heterogeneous Interactions in SoC Verification

This paper presents a novel modelling methodology for system-on-chip (SoC) verification based on software techniques. This methodology facilitates the automation of test generation; it also enables the focuses being placed on system-level behaviors such as concurrency and resource-contentions. We have demonstrated the feasibility to generalize heterogeneous interactions systematically and use them as the building blocks to generate complex test-cases of real-world concurrency