A VHDL Generation Tool for Optimized Parallel FIR Filters

This paper presents generation tool and performance results on a method to minimize the amount of hardware needed to implement a parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation targeted for high performance. The generation tool employ a combination of two approaches: first, the reduction of the coefficients to n-power-of-two (NPT) terms, using cannonical signed digit (CSD) as an option, followed by common subexpression elimination (CSE) among multipliers. Synthesis results for a range of different filter specifications, using Quartus II FPGA synthesis tool and Cadence PKS standard cell synthesis tool are presented