Derivation of signal flow directions and synchronizers for switch-level timing analysis

Signal flow directions and synchronizers in switch-level circuits are useful information in both simulation and timing analysis. Since signal flow of a transistor may get changed at different clock phases, our new approach of assigning signal flow directions incorporates with synchronizers. Our algorithm takes a global approach by assigning signal flow directions and synchronisers of transistors simultaneously from the graphical representation of a circuit. In our approach, functionality of a circuit is considered to determine signal flow directions, synchronizers, and feasible transitions. Our experimental results show that our algorithm is effective in both static and dynamic CMOS circuits with reasonable time and space